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Title:
Exploring the Development Trend of High Performance Interconnection Networks |
Abstract:
High-performance interconnection network is the key to realize high-speed collaborative parallel computing in high-performance computing (HPC) system. Its performance directly affect the efficiency and scalability of the HPC system. With the continuous performance improvement of HPC systems, the development trend of high-performance interconnection network is mainly reflected in the network size and network bandwidth. With the slowdown of the development of Moore's Law, high-performance interconnection networks face enormous challenges in terms of power consumption, density, scalability, reliability, and cost. It is necessary to adopt new packaging technology and new design technology to design and implement high-performance interconnection network for HPC. The report first analyzes the state-of-the-art representative high-performance interconnection network in the Top500 list, including Nvidia Infiniband, Intel Omni-Path, Cray Slingshot/Aries, and Custom/Proprietary networks including Fugaku Tofu, Bull BXI, TH-Express et al. Based on the analysis of the challenges faced by high-performance interconnection networks design in the post-Moore era and the exascale computing era, this report finally presents the perspective of high-performance interconnection networks. |
Biography:
Lu Pingping, an associate researcher at the School of Computer Science at the University of National Defense Technology, has been engaged in the development of high-performance computer systems for over ten years. As a key member, she has participated in the development of multiple generations of Galaxy/Tianhe high-performance computer systems, mainly focusing on computer system architecture and high-performance interconnection networks. She has received two first prizes military progress prize in science and technology, published over 40 academic papers, more than 30 invention patents, including 3 American patents, 6 computer software copyrights and 1 integrated circuit layout design. |